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DS1742 y2kc nonvolatile timekeeping ram DS1742 preliminary 061998 1/13 features ? integrated nv sram, real time clock, crystal, power- fail control circuit and lithium energy source ? clock registers are accessed identical to the static ram. these registers are resident in the eight top ram locations. ? century byte register ? totally nonvolatile with over 10 years of operation in the absence of power ? bcd coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year com- pensation valid up to the year 2100 ? battery voltage level indicator flag ? powerfail write protection allows for 10% v cc power supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? standard jedec bytewide 2k x 8 static ram pinout ? quartz accuracy 1 minute a month @ 25 c, factory calibrated ordering information DS1742xxx 70 70 ns access 100 ns access 100 (5 volt) DS1742wxxx 120 120 ns access 150 ns access 150 (3.3 volt) pin assignment a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v cc a8 a9 we oe a10 ce dq7 dq6 dq5 dq4 dq3 pin description a0a10 address inputs ce chip enable oe output enable we write enable v cc power supply input gnd ground dq0dq7 data input/outputs description the DS1742 is a full function, year 2000 compliant (y2kc), realtime clock/calendar (rtc) and 2k x 8 nonvolatile static ram. user access to all registers within the DS1742 is accomplished with a bytewide interface as shown in figure 1. the real time clock (rtc) information and control bits reside in the eight up- permost ram locations. the rtc registers contain century, year, month, date, day, hours, minutes, and se- conds data in 24 hour bcd format. corrections for the day of the month and leap year are made automatically. the rtc clock registers are double buffered to avoid access of incorrect data that can occur during clock up- date cycles. the double buffered system also prevents time loss as the timekeeping countdown continues un- abated by access to time register data. the DS1742 also contains its own powerfail circuitry which dese- lects the device when the v cc supply is in an out of toler- ance condition. this feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided.
DS1742 061998 2/13 clock operationsreading the clock while the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a one is written into the read bit, bit 6 of the century register, see table 2. as long as a one remains in that position, updating is halted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the DS1742 registers are updated simultaneously af- ter the internal clock register updating process has been reenabled. updating is within a second after the read bit is written to zero. DS1742 block diagram figure 1 oscillator and clock countdown chain power monitor, switching, and write protection v cc clock registers 2k x 8 ce we a0a10 dq0dq7 32.768 khz + oe v bat nv sram DS1742 truth table table 1 v cc ce oe we mode dq power itl v ih x x deselect highz standby in tolerance v il x v il write data in active i n t o l erance v il v il v ih read data out active v il v ih v ih read highz active v bat x x x deselect highz cmos standby DS1742 registers. the user can then load them with the correct day, date and time data in 24 hour bcd format. resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume.
DS1742 061998 3/13 stopping and starting the clock oscillator the clock oscillator may be stopped at any time. to in- crease the shelf life, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb (bit 7) of the seconds registers, see table 2. setting it to a one stops the oscillator. frequency test bit as shown in table 2, bit 6 of the day byte is the frequency test bit. when the frequency test bit is set to logic a1o and the oscillator is running, the lsb of the seconds register will toggle at 512 hz. when the seconds register is be- ing read, the dq0 line will toggle at the 512 hz frequency as long as conditions for access remain valid (i.e., ce low, oe low, we high, and address for seconds register remain valid and stable). clock accuracy the DS1742 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. the clock is cali- brated at the factory by dallas semiconductor using special calibration nonvolatile tuning elements. the DS1742 does not require additional calibration and tem- perature deviations will have a negligible effect in most applications. for this reason, methods of field clock cal- ibration are not available and not necessary. DS1742 register map table 2 address data function/range address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 7ff 10 year year year 0099 7fe x x x 10 mo month month 0112 7fd x x 10 date date date 0131 7fc bf ft x x x day day 0107 7fb x x 10 hour hour hour 0023 7fa x 10 minutes minutes minutes 0059 7f9 osc 10 seconds seconds seconds 0059 7f8 w r 10 century century century 0039 osc = stop bit r = read bit ft = frequency test w = write bit x = see note below bf = battery flag note: all indicated axo bits are not dedicated to any particular function and can be used as normal ram bits. retrieving data from ram or clock the DS1742 is in the read mode whenever oe (output enable) is low, we (write enable) is high, and ce (chip enable) is low. the device architecture allows ripple- through access to any of the address locations in the nv sram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce , and oe access times and states are satisfied. if ce , or oe access times and states are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce , and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce , and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the DS1742 is in the write mode whenever we , and ce are in their active state. the start of a write is referenced to the latter occurring transition of we , on ce . the ad- dresses must be held valid throughout the cycle. ce , or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for
DS1742 061998 4/13 t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then dis- able the outputs t wez after we goes active. data retention mode the 5 volt device is fully accessible and data can be writ- ten or read only when v cc is greater than v pf . however, when v cc is below the power fail point, v pf , (point at which write protection occurs) the internal clock regis- ters and sram are blocked from any access. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3 volt device is fully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below the power fail point, v pf , access to the device is inhibited. if v pf is less than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v bat , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v bat . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. battery longevity the DS1742 has a lithium power source that is de- signed to provide energy for clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. for specification pur- poses, the life expectancy is 10 years at 25 c with the internal clock oscillator running in the absence of v cc power. each DS1742 is shipped from dallas semicon- ductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the DS1742 will be much longer than 10 years since no lithium battery energy is consumed when v cc is present. battery monitor the DS1742 constantly monitors the battery voltage of the internal battery. the battery flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. this bit is not writable and should always be a one when read. if a zero is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc and ram are questionable.
DS1742 061998 5/13 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +6.0v operating temperature 0 c to 70 c storage temperature 20 c to +70 c soldering temperature 260 c for 10 seconds (see note 7) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 voltage all inputs v cc = 5v 10% v ih 2.2 v cc +0.3v v 1 v cc = 3.3v 10% v ih 2.0 v cc +0.3v v 1 logic 0 voltage all inputs v cc = 5v 10% v il 0.3 0.8 v 1 v cc = 3.3v 10% v il 0.3 0.6 v 1 dc electrical characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current (ce = v ih ) i cc1 1 3 ma 2, 3 cmos standby current (ce v cc 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il 1 +1 m a output leakage current (any output) i ol 1 +1 m a output logic 1 voltage (i out = 1.0 ma) v oh 2.4 1 output logic 0 voltage (i out = +2.1 ma) v ol 0.4 1 write protection voltage v pf 4.25 4.37 4.50 v 1 battery switch over voltage v so v bat 1, 4
DS1742 061998 6/13 dc electrical characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current (ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos standby current (ce vcc 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il 1 +1 m a output leakage current (any output) i ol 1 +1 m a output logic 1 voltage (i out = 1.0 ma) v oh 2.4 1 output logic 0 voltage (i out = 2.1 ma) v ol 0.4 1 write protection voltage v pf 2.80 2.88 2.97 v 1 battery switch over voltage v so v bat or v pf v 1, 4 read cycle, ac characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol 70 ns access 100 ns access units notes parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq lowz t cel 5 5 ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq lowz t oel 5 5 ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 5 5 ns
DS1742 061998 7/13 read cycle, ac characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol 120 ns access 150 ns access units notes parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce low to dq lowz t cel 5 5 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns oe low to dq lowz t oel 5 5 ns oe access time t oea 100 130 ns oe data off time t oez 35 35 ns output hold from address t oh 5 5 ns read cycle timing diagram a0a10 ce oe dq0dq7 t rc t aa t cea t cel t oea t oel valid t oh t cez t oez
DS1742 061998 8/13 write cycle, ac characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol 70 ns access 100 ns access units notes parameter symbol min max min max units notes write cycle time t wc 70 100 ns address setup time t as 0 0 ns we pulse width t wew 50 70 ns ce pulse width t cew 55 75 ns data setup time t ds 30 40 ns data hold time t dh 0 0 ns address hold time t ah 0 0 ns we data off time t wez 25 35 ns write recovery time t wr 5 5 ns write cycle, ac characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol 120 ns access 150 ns access units notes parameter symbol min max min max units notes write cycle time t wc 120 150 ns address setup time t as 0 0 ns we pulse width t wew 100 130 ns ce pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh 0 0 ns address hold time t ah 0 0 ns we data off time t wez 40 50 ns write recovery time t wr 10 10 ns
DS1742 061998 9/13 write cycle timing diagram,write enable controlled a0a10 ce we dq0dq7 t wc t as t wew t wez valid t wr valid data output data input data input t as t ah t ds t dh write cycle timing diagram, ce , controlled a0a10 ce we dq0dq7 t wc t as valid t wr valid data input data input t ah t ds t dh t as t cew
DS1742 061998 10/13 powerup/down ac characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min typ max units notes ce or we at v ih , ce2 at v il , before powerdown t pd 0 m s v cc fall time: v pf (max) to v pf (min) t f 300 m s v cc fall time: v pf (min) to v so t fb 10 m s v cc rise time: v pf (min) to v pf (max) t r 0 m s powerup recover time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5, 6 powerup/down waveform timing 5 volt device v cc t fb inputs t f v pf (max) v pf (min) t r v so t pd t dr t rec outputs don't care highz recognized valid recognized
DS1742 061998 11/13 powerup/down characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol min typ max units notes ce or we at v ih , before powerdown t pd 0 m s v cc fall time: v pf(max) to v pf(min) t f 300 m s v cc rise time: v pf(min) to v pf(max) t r 0 m s powerup recovery time t rec 35 ms expected data retention time (oscillator on) t dr 10 years 5, 6 powerup/down waveform timing 3.3 volt device v cc inputs t f v pf(max) v pf(min) t r t pd t rec outputs don't care highz recognized valid valid recognized capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all input pins c in 7 pf capacitance on all output pins c o 10 pf
DS1742 061998 12/13 ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0.0 to 3.0 volts timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1. voltages are referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. battery switch over occurs at the lower of either the battery terminal voltage or v pf . 5. data retention time is at 25 c. 6. each DS1742 has a builtin switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 7. realtime clock modules can be successfully processed through conventional wavesoldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used to prevent damage to the crystal.
DS1742 061998 13/13 DS1742 24pin package 1 c f g k d h b e j a dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.270 37.34 1.290 37.85 0.675 17.15 0.700 17.78 0.315 8.00 0.335 8.51 0.075 1.91 0.105 2.67 0.015 0.38 0.030 0.76 0.140 3.56 0.180 4.57 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.010 0.25 0.018 0.45 0.015 0.43 0.025 0.58 24pin pkg

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